Fully Digital Capacitance-to-Digital Converter Using Iterative Delay-Chain Discharge

نویسندگان

  • Wanyeong Jung
  • Seokhyeon Jeong
  • Sechang Oh
  • Dennis Sylvester
  • David Blaauw
چکیده

Capacitance sensors are widely used to measure various physical quantities, including position, pressure, and concentration of certain chemicals [1-6]. Integrating capacitive sensors into a small wireless sensor system is challenging due to their large power consumption relative to the total system power/energy budget, which can be as low as a few nW [4]. Typical capacitance-to-digital converters (CDCs) use charge sharing or charge transfer between capacitors to convert the sampled capacitance to voltage, which is then measured with an ADC [1-6]. This approach requires complex analog circuits, such as amplifiers and ADCs, increasing design complexity and often increasing power consumption. Moreover, the initial capacitance to voltage conversion essentially limits the input capacitance range because of output voltage saturation. This paper presents a fully digital CDC that is based on the observation that when a ring oscillator (RO) is powered from a charged capacitance, the number of RO cycles required to discharge the capacitance to a fixed voltage is naturally linear with the capacitance value. This observation enables a simple, fully digital conversion scheme that is inherently linear. As a result, the proposed CDC performs conversion across a very wide capacitance range from 0.7pF to over 10nF with < 0.06% linearity error. The CDC senses 11.3pF input capacitance with 35.1pJ conversion energy and 141fJ/c-s FoM.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

A 0.84ps-LSB 2.47mW Time-to-Digital Converter Using a Charge Pump and a SAR-ADC

We propose a time-to-digital converter (TDC) using a charge pump and a SAR-ADC. With this architecture, high time resolution is attainable by increasing the charging current or reducing the sampling capacitance. Thus, the resolution limitation in a delay-chain TDC does not exist. We propose to use a SAR-ADC attributed to its characteristics of compact structure, scalability, low power consumpti...

متن کامل

Time-to-Digital Converter (TDC) with Sub-ps-Level Resolution using Current DAC and Digitally Controllable Load Capacitor

This paper describes a cyclic time domain successive approximation (CTDSA) architecture that can be used as an interpolator in a time-to-digital converter (TDC). The new architecture of the CTDSA achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range. The propagation delay adjustment is implemented by digitally controlling both the unit load capacitors and the...

متن کامل

Fully Integrated Low-Noise Readout Circuit with Automatic Offset Cancellation Loop for Capacitive Microsensors

Capacitive sensing schemes are widely used for various microsensors; however, such microsensors suffer from severe parasitic capacitance problems. This paper presents a fully integrated low-noise readout circuit with automatic offset cancellation loop (AOCL) for capacitive microsensors. The output offsets of the capacitive sensing chain due to the parasitic capacitances and process variations a...

متن کامل

Digital Controller Designbased on Time Domain for DC-DC Buck Converter

In this paper, the digital controller design for compensating the dc-dc buck converter output voltage has been analyzed in the digital domain. The main idea of this paper is patterning the samples of high order ideal controller and using integral square error in determining digital PID coefficients. This approach provides higher precision of digital controller design and eliminates the need for...

متن کامل

Adaptive Signal to Noise Ratio Scalable Analog Front-End Continuous Time Sigma Delta Converter For Digital Hearing Aids by

i ABSTRACT A dual-channel directional digital hearing aid (DHA) front end using Micro Electro Mechanical System (MEMS) microphones and an adaptive-power analog processing signal chain is presented. The analog front end consists of a double differential amplifier (DDA) based capacitance to voltage conversion circuit, 40dB variable gain amplifier (VGA) and a continuous time sigma delta analog to ...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2015